As AI clusters scale, the network interfaces increasingly determine accelerator utilization, latency, congestion management, and infrastructure efficiency.
Hyperscalers must balance distinct frontend and AI backend networking requirements while keeping pace with increasing bandwidth demands, growing software complexity, and tighter power and system constraints. At large-scale AI, the interface becomes a place to compete. Proprietary control over packet processing, offload, telemetry, security, host connectivity, and network evolution turns the endpoint from a commodity into a source of differentiation.
Marvell brings networking technology and custom silicon execution together to develop interfaces around specific workload, XPU, software, and infrastructure requirements. The result is greater control over network performance, system integration, infrastructure processing, and the connectivity roadmap as AI systems scale.
Technology Building Blocks
High-Speed Serializer-Deserializer (SerDes)
Reach and bandwidth for demanding data center links
Reach and bandwidth for demanding data center links
AI clusters require network bandwidth to grow alongside XPU performance. As interface speeds rise, power per bit, signal integrity, reach, and bandwidth density become critical design considerations.
Marvell high-speed SerDes provides the electrical foundation for custom network interfaces, with 224G SerDes supporting next-generation Ethernet connectivity across demanding data center channels.
What it enables:
Higher aggregate network bandwidth
Greater bandwidth per lane
More efficient use of package and board resources
Long-reach electrical connectivity
Lower power per delivered bit
Marvell develops SerDes as part of a broader connectivity portfolio spanning custom silicon, Ethernet switching, electrical interconnect, and optics. This provides system-level visibility into the full path from the network interface through the physical link.
Ethernet MAC and PCS
Optimize the Ethernet data path for AI traffic
Optimize the Ethernet data path for AI traffic
Higher port speed alone does not ensure efficient AI networking. The Ethernet data path must also handle sustained traffic while meeting requirements for latency, congestion, reliability, traffic distribution, and telemetry.
Marvell Ethernet MAC (media access control) and PCS (physical coding sublayer) technology provides the protocol and data path foundation for custom frontend and AI backend network interfaces.
Custom architectures can address:
RDMA-oriented data movement
Queue and congestion management
Multipath traffic distribution
Loss and retry behavior
Fine-grained telemetry
Application-specific transport and scheduling
These capabilities can be combined with customer-developed packet-processing and traffic-management functions to align the interface with workload and deployment requirements. Support for evolving Ethernet-based AI networking standards can also be incorporated as architectures advance.
Hardened Arm Cores and Packet Processing
Put infrastructure processing in the right place
Put infrastructure processing in the right place
AI infrastructure requires networking, security, storage, virtualization, telemetry, and management functions alongside application and AI compute. Running these services on host processors can consume resources better used for differentiated workloads.
Marvell hardened Arm cores and packet-processing capabilities provide a programmable foundation for custom NIC and SmartNIC architectures.
Functions include:
Packet and flow processing
Network virtualization
Multi-tenancy
Crypto and security
Storage acceleration
Traffic management
Telemetry and diagnostics
Customer-specific infrastructure services
Functions can be distributed across programmable cores, dedicated hardware acceleration, and host software based on performance, power, flexibility, and isolation requirements. This allows the architecture to be shaped around the level of programmability and offload required rather than around a predefined SmartNIC design.
PCIe and Ethernet Chiplets with D2D
Bring connectivity closer to the XPU
Bring connectivity closer to the XPU
Network interfaces no longer have to remain discrete devices on the board. As AI systems adopt multi-die architectures, networking and I/O functions can be partitioned into specialized chiplets and placed closer to the XPU.
Marvell PCIe and Ethernet chiplets, combined with high-bandwidth die-to-die connectivity, provide more flexibility in how connectivity is integrated with compute.
Architecture options include:
Conventional PCIe-attached interfaces
In-package Ethernet and I/O chiplets
High-bandwidth D2D connectivity
Independent optimization of compute and I/O
Reuse of connectivity chiplets across XPU generations
Different process technologies for compute and connectivity
Chiplet partitioning can also reduce pressure on valuable compute die area while allowing networking technology to evolve on its own roadmap.
Resources
Marvell Delivers Advanced Packaging Platform for Custom AI Accelerators
Learn More
Marvell and NVIDIA to Provide Custom Solutions for Advanced AI Infrastructure
Learn More
Custom Compute in the AI Era
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AI Accelerators FAQs
What is a custom network interface?
A custom network interface is purpose-built silicon that connects CPUs, XPUs, servers, or storage systems to the network. Designs can range from high-performance AI NICs to programmable SmartNICs, with connectivity, processing, offload, telemetry, security, and software functions shaped around specific infrastructure requirements.
When does a custom network interface make sense instead of a merchant device?
Merchant NICs and DPUs are well suited when existing architectures meet performance, feature, and roadmap requirements. Custom becomes more compelling when deployment scale justifies greater control over data path behavior, infrastructure offload, telemetry, security, host or XPU connectivity, power, system economics, or future generations.
How do frontend and AI backend network interfaces differ?
Frontend interfaces connect AI systems to applications, storage, services, and the broader data center. AI backend interfaces support intensive east-west communication between accelerator systems, placing greater emphasis on sustained bandwidth, low tail latency, congestion management, loss handling, and efficient accelerator data movement.
What technology does Marvell bring to custom network interfaces?
Core technologies include high-speed SerDes, Ethernet MAC and PCS, hardened Arm cores with packet processing, and PCIe and Ethernet chiplets with die-to-die connectivity. These technologies can be combined with additional Marvell, customer-developed, and third-party IP based on system requirements.
Can proprietary networking technology be incorporated into the design?
Yes. Custom programs can incorporate proprietary RTL, packet-processing functions, traffic-management algorithms, accelerators, firmware, security technology, and other differentiated capabilities. Engagements can begin from an existing architecture, detailed specifications, or a jointly developed design.
Can networking functions move closer to the XPU?
Yes. PCIe remains an important host interface, while chiplet and die-to-die architectures create additional options for positioning Ethernet and I/O functions closer to compute. This can support higher in-package bandwidth, reuse of connectivity technology, and independent evolution of compute and I/O.
How does Marvell’s broader networking portfolio benefit a custom interface program?
Network interfaces interact directly with switches, electrical channels, optics, and the wider fabric. Marvell expertise across Ethernet switching, SerDes, electrical connectivity, optical DSPs, silicon photonics, and custom silicon provides broader system context for endpoint architecture decisions.
How does Marvell support the development process?
Marvell can support architecture definition, IP development and integration, front-end and physical design, packaging, validation, manufacturing, and volume deployment. Depending on the program, support can also extend to board-level implementation.
How early should a custom network interface program begin?
Early engagement creates more opportunity to optimize the interface alongside the XPU topology, traffic model, software architecture, bandwidth requirements, power envelope, package, and network roadmap. Decisions made before the architecture is fixed can have significant impact on performance, integration, and program economics.
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