For massive AI workloads, purpose-built silicon consistently outperforms general-purpose architectures. Custom AI accelerators (XPUs) maximize performance-per-watt, expand usable memory per socket, and give hyperscalers unprecedented control over data center economics.
Marvell co-designs XPUs around specific workload and deployment requirements, combining customer-developed compute with Marvell IP across interconnect, memory, and packaging, supported by implementation expertise from architecture through production.
The accelerator is designed from a system perspective, balancing memory bandwidth, die partitioning, package architecture, scale-up connectivity, and rack-level requirements within a broader multi-vendor ecosystem.
Technology Building Blocks for AI Accelerator Design
Serializer-Deserializer (SerDes)
Support High-Bandwidth Accelerator I/O
Support High-Bandwidth Accelerator I/O
AI accelerators require high-speed interfaces to connect with scale-up fabrics, retimers, copper links, and optical systems. Marvell SerDes technology provides the electrical foundation for high-bandwidth accelerator connectivity.
- High-speed roadmap: Production-proven 224G SerDes, with 448G technology for future bandwidth requirements.
- Reach options: Support for board, backplane, copper cable, and optical connectivity requirements.
- Proven reliability: Deep experience in signal integrity, bit error rate, power, and channel optimization.
This helps hyperscalers match accelerator I/O to the bandwidth, reach, and power requirements of the system.
Die-to-Die (D2D)
Connect Compute, Memory, and I/O Across Multiple Dies
Connect Compute, Memory, and I/O Across Multiple Dies
Scaling multi-die accelerators requires massive bandwidth between compute, memory, and I/O dies without exhausting power budgets or die-edge real estate. Marvell 2nm D2D IP delivers breakthrough efficiency.
- Massive bandwidth density: Achieves over 30 Tbps/mm (more than 3X the density of UCIe at equivalent speeds), with 64 Gbps per wire bidirectional signaling.
- Exceptional power savings: Delivers up to 75% lower interface power under normal workloads and up to 42% lower at peak.
- Built-in resilience: Features redundant lanes and automatic lane repair for maximum reliability.
By reducing the power and area required to move data between dies, Marvell die-to-die technology gives architects greater flexibility to partition accelerator functions across the package.
Dense SRAM
Use More of the Die for Compute and High-Bandwidth Memory
Use More of the Die for Compute and High-Bandwidth Memory
AI accelerators require substantial on-chip memory, but SRAM can consume significant die area and standby power. Marvell dense SRAM gives architects flexibility in how silicon and power are allocated across compute, memory, and workload-specific functions.
- High capacity and speed: Supports up to 6 Gb of high-speed SRAM operating at up to 3.75 GHz.
- Area efficiency: Recovers up to 15% of totalthe total 2nm die area compared with standard implementations.
- Lower standby power: Reduces standby power by up to 66% versus standard on-chip SRAM at equivalent density.
By reducing on-chip memory overhead, Marvell dense SRAM can free area and power for additional compute, larger memory capacity, or other accelerator-specific features.
Scale Out
Integrate Larger Multi-Die Accelerators
Integrate Larger Multi-Die Accelerators
Reticle limits mean a single monolithic die can no longer hold enough compute, memory, and I/O for a frontier accelerator. Package architecture directly affects bandwidth, power delivery, thermals, yield, test, manufacturability, and supply. Marvell advanced packaging assembles multiple optimized dies into one accelerator that behaves as a single system.
- Multi-die integration at scale: 2.5D, 3.5D, and 3D options, including 3D SOIC on N2P and N3P nodes, holding up to 16x more compute cores than a conventional monolithic package.
- Integrated optics and advanced power delivery: Enables co-packaged optics as bandwidth and reach exceed practical copper limits. Advanced power delivery shortens the path between voltage regulation and compute silicon, reducing losses and helping support higher-density accelerator packages.
- Partnerships and supply flexibility: A proven path from advanced foundry packaging to qualified OSAT and RDL alternatives, backed by relationships across substrate, component, and memory suppliers.
Marvell makes packaging a first-order design choice, helping hyperscalers integrate more compute and memory while balancing performance, manufacturing, and supply.
Resources
Marvell Delivers Advanced Packaging Platform for Custom AI Accelerators
Learn More
Marvell and NVIDIA to Provide Custom Solutions for Advanced AI Infrastructure
Learn More
Custom Compute in the AI Era
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AI Accelerators FAQs
What is a custom AI accelerator (XPU)?
A workload-optimized compute engine that Marvell co-designs with a single hyperscaler, built as a multi-die system in a package. It integrates your IP with Marvell foundational IP, surrounded by high-bandwidth memory, dense on-chip SRAM, and high-speed I/O.
Why are hyperscalers developing custom AI accelerators?
Hyperscalers operate AI workloads at volumes where architecture choices can materially affect performance, power, and economics. AI accelerators allow compute, precision, memory hierarchy, I/O, and packaging to be aligned with defined workload and deployment requirements.
How can hyperscalers preserve their own compute differentiation?
Customer-developed compute can remain central to the accelerator. Marvell can provide selected chiplets, IP, packaging, implementation, and production expertise around that differentiated compute architecture.
How does Marvell engage in an AI accelerator program?
Marvell can support design-to-spec, co-development, or a combination of both. This allows different parts of the accelerator to use different engagement models based on technical ownership, integration complexity, and customer priorities.
Why is early architecture engagement important?
Memory hierarchy, die partitioning, I/O, power, and packaging affect one another. Early engagement allows these decisions to be evaluated together before physical boundaries and interfaces are fixed.
How does the Marvell process roadmap support AI accelerators?
Marvell has demonstrated working TSMC 2nm silicon and developed 2nm technologies such as dense SRAM and high-bandwidth D2D. Development also extends to TSMC A14 for future accelerator generations.
How does Marvell support multi-die accelerator design?
Marvell combines D2D, SerDes, dense SRAM, advanced packaging, physical implementation, power, thermal, test, and manufacturing expertise to help integrate compute, memory, and I/O across multiple dies.
How does Marvell help with rack-level performance?
Accelerator I/O is considered in the context of scale-up fabrics, network interfaces, switching, copper links, and optical connectivity. This helps align the accelerator with the system where it must operate.
What happens after tapeout?
The accelerator moves through silicon bring-up, characterization, manufacturing test, package qualification, reliability testing, yield improvement, and production qualification. Marvell also helps coordinate supply dependencies such as HBM, substrates, packaging, and test capacity.
How does Marvell reduce program risk?
Through depth in verification and test: simulation, design verification, hardware emulation, DFT, shift-left test development, reliability testing, and package qualification. System-level test confirms the device performs its intended function in your system, which is distinct from manufacturing test.
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