Use cases for the technology include connecting XPUs or switch silicon within a tray to maximize compute density or connecting servers within a rack via a copper backplane: up to 512 lanes of the 224G LR SerDes could be integrated into a 102.4T switch.¹ The 224G LR SerDes is capable of being incorporated into CPC cables, near-packaged optics, co-packaged optics and chip-to-memory subsystems. Marvell has demonstrated performance of 4 picojoules per bit.¹

Why SerDes Matters

Think of SerDes technology as the molecule of networking: the irreducible, irreplaceable component upon which larger systems are built. A circuit block inside XPUs, switches, high-speed interfaces like PCIe, optical components and other devices, SerDes transform parallel data streams into serial data to reduce the number of communication channels between chips in different devices or between die within the same chip. Reducing lanes reduces pin count and complexity while enhancing signal integrity. The quality of SerDes IP also has a fundamental impact on power consumption, speed, latency, bandwidth and link length.

SerDes performance also has a vital impact on total cost of ownership and return on investment. Lowering power consumption by a single picojoule per bit on a 200G/lane device can reduce system power consumption by up to 100 watts, giving hyperscalers the ability to lower operating costs and/or dedicate existing power capacity to revenue-generating activities like inference services.¹

The Marvell® SerDes portfolio ranges from die-to-die interconnects for linking die within advanced packaging to optical SerDes capable of sending data over 2 kilometers. Marvell has also regularly published papers and technological firsts with IEEE, ISSCC and other organizations on SerDes breakthroughs. Over the past several years, Marvell has also doubled the line speed rate of its leading SerDes approximately every two years. Last year, Marvell demonstrated the industry’s first 400G/lane technology with a complete electrical to optical link, a technology once considered impossible.²

“Why is SerDes so difficult? Think of it like this: if you want to transport millions of passengers, you could use a multi-lane highway with many cars going 60 miles per hour. But if you want to go faster, you’d use a high-speed bullet train traveling at 300 miles per hour—faster, but still reliable,” said Sandeep Bharathi, President of the Data Center Group at Marvell, at the Marvell Custom AI Investor Event in 2025. “SerDes works the same way. It must transfer multiple bits at gigabit speeds over long distances—across cables—with the lowest power and lowest latency. You need to move data from one chip to another very quickly, without losing bits. This level of innovation takes a very talented team and years of experience analyzing silicon results to continue pushing the boundaries across all performance metrics.”

Interconnect technology is in the middle of a historical transformation with the escalating performance requirements of AI. Through an ecosystem-driven approach, Marvell and partners like Luxshare-Tech will collaborate to accelerate product development, expand customer choice, and streamline the adoption and integration of new technologies for data infrastructure.

1. Marvell internal estimates.
2. Marvell press release, March 31, 2025.

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