Marvell Presents at DesignCon 2023
Where the Chip Meets the Board
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Join Marvell and industry thought leaders at DesignCon, the high-speed communications and system design conference and exposition.
Presentations and Panels
Title: The Case of the Closing Eyes - Bridging FEC to Signal Integrity
Description: Forward Error Correction (FEC) is a key enabler for High Speed communications designs. This panel of experts will discuss the role FEC plays and how it can be impacted by signal integrity challenges; and what to do with a testing architecture designed to help find a bridge between FEC and Signal Integrity.
Format: Panel Discussion
Date/Time: Tuesday, January 31 at 4:45 pm - 6:00 pm
Location: Ballroom GH
Marvell Presenter: Mark Marlett, Senior Principal System Engineer
Title: Panel – FEC for Next Generation 800G/1.6T Ethernet Systems
Description: To meet the next-generation system performance requirement, IEEE 802.3df task force has been investigating and discussing the need and options of forward error correction (FEC) for next generation Ethernet system with 100Gbps and 200Gbps lane speeds. Join this panel of experts for a lively panel discussion on FEC for 800G/1.6T Ethernet system. This panel will present the work on the 800GE and 1.6TE PCS/FEC including the use-cases for 100G and 200G lanes, drivers for the different PCS/FEC proposals, pros/cons of the different approaches, FEC performance analysis with different architectures and decoding schemes, and the FEC option that each panelist supports. It will provide the audience an opportunity to hear and discuss new FEC technologies and industry and standard bodies' latest developments.
Date/Time: Thursday, February 2 at 4:00 pm - 5:15 pm
Location: Ballroom G
Marvell Presenter: Kapil Shrikhande, Distinguished Engineer
Marvell 展台信息
January 31-February 2, 2023
Santa Clara Convention Center
加利福尼亚州圣克拉拉市
